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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:22:58 03/11/2011 
-- Design Name: 
-- Module Name:    Interrupt_Reg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
library work;
use work.Definitions.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following library declaration if instantiating
--any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Interrupt_Reg is
    Port ( clk_i        : in   STD_LOGIC;
           clr_i        : in   STD_LOGIC;
           pc_in        : in   STD_LOGIC_VECTOR (9 downto 0);
           flags_in     : in   STD_LOGIC_VECTOR (1 downto 0);
           int_req      : in   STD_LOGIC;
			  op_code      : in   STD_LOGIC_VECTOR(2 downto 0);
			  proc_state	: in	 processor_state;
			  is_misc      : in   STD_LOGIC;
           pc_out 		: out  STD_LOGIC_VECTOR (9 downto 0);
           flags_out    : out  STD_LOGIC_VECTOR (1 downto 0);
           int_enable   : out  STD_LOGIC);
end Interrupt_Reg;

architecture Behavioral of Interrupt_Reg is

begin 
	Interruption_Reg : process(clk_i,clr_i,int_req)
		begin
			if(clr_i = '1') then
				int_enable <= '0';
			else if rising_edge(clk_i) then
				if (proc_state = interrupt) then
					pc_out <= pc_in;
					flags_out <= flags_in;
					int_enable <= '0';
				else if ((proc_state = decode) and (is_misc = '1')) then 
					if (int_req = '1') then
						if (op_code = "010" or op_code = "001") then 
							int_enable <= '1';
						else if (op_code = "011") then 
							int_enable <= '0';
							  end if;
						end if;
					end if;
				end if;
				end if;
			end if;
			end if;
		end process;
		 
end Behavioral;
